A vertical type MOSFET (i.e., metal-oxide semiconductor field effect transistor) having a trench gate electrode has low on-state resistance and high withstand voltage. Therefore, the vertical type MOSFET is suitably used for a switching device in power electronic equipment. When the on-state resistance and the withstand voltage are improved much more, a relationship between the on-state resistance and the withstand voltage shows a trade-off relationship. Specifically, when the on-state resistance is reduced, the withstand voltage decreases. When the withstand voltage is increased, the on-state resistance increases.
In view of the above trade-off relationship, a vertical type MOSFET having a trench gate electrode with a super junction construction is disclosed in Japanese Patent Application Publications No. H09-266311 (i.e., U.S. Pat. No. 6,294,818) and No. 2000-260984.
As shown in FIG. 1, a semiconductor device 1 disclosed in Japanese Patent Application Publication No. H09-266311 has a MOSFET with a drift region 23 having a super junction construction. The device 1 includes a source region 32, a body region 30, the drift region 23, a drain region 22, and a trench gate electrode 36. The source region 32 has N type conductivity, and connects to a source power supply S. The body region 30 has P type conductivity, and separates between the source region 32 and the drift region 23. The drift region 23 includes a P type column 24 and an N type column 26. The P type column 24 extends between a body region 30 and a drain region 22. The N type column 26 adjacent to the P type column 24 extends between the body region 30 and the drain region 22. The P type column 24 and the N type column 26 are combined so that they provide an alternation of strata, (i.e., an alternate layer). The alternate layer is repeated alternately so that the drift region 23 is formed. The drain region 22 has the N type conductivity, and the drain region 22 is connected to a drain power supply D through the drain electrode 20. A trench gate electrode 36 penetrates the body region 30, and reaches the drift region 23. The body region 30 separates between the source region 32 and the drift region 23. The trench gate electrode 36 extends in a repeat direction, in which the alternate layer of the P type column 24 and the N type column 26 is repeated alternately. The trench gate electrode 36 faces a semiconductor region composed of the source region 32, the body region 30, and the drift region 23 through an insulation layer 34. The trench gate electrode 36 is connected to a gate power supply G.
When the trench gate electrode 36 of the semiconductor device 1 is applied with positive voltage, an inversion layer is formed in the body region 30 having the P type conductivity, which faces a side of the trench gate electrode 36. The inversion layer of the body region 30 becomes a channel. Therefore, electrons supplied to the source region 32 from the source power supply S pass through the channel of the body region 30 and the N type column 26, and then, flows toward the N type drain region 22.
When the trench gate electrode 36 is grounded, no inversion layer is formed in the P type body region 30 facing the side of the trench gate electrode 36. Therefore, the semiconductor device 1 becomes off state. When the source voltage and the gate voltage are set to be zero Volts, and an inversion bias voltage is applied to the semiconductor device 1, a depletion layer extends in the P type column 24 and the N type column 26 from a P-N junction surface between the P type column 24 and the N type column 26. Here, the drain voltage is set to be a positive voltage. At this time, each impurity concentration of the P type column 24 and the N type column 26 and a column width (i.e., a pitch in the repeat direction) of them are disposed in an appropriate range, the depletion layer expands uniformly in the whole area of the P type column 24 and the N type column 26, so that the whole area of them is completely depleted substantially. Thus, the off state withstand voltage becomes high.
The on state resistance of the semiconductor device 1 is the sum of a channel resistance, a drift resistance and a resistance of the N type drain region 22. The channel resistance is a resistance of the channel formed around the trench gate electrode 36. Specifically, the channel resistance is the resistance of the channel of the body region 30. The drift resistance is a resistance of the N type column 26. In the vertical type MOSFET shown in FIG. 1, the drift resistance constitutes a large percentage of the on state resistance of the semiconductor device 1. Therefore, it is effective to reduce the drift resistance for reducing the on state resistance of the semiconductor device 1. Specifically, the on state resistance of the N type column 26 can be reduced by increasing the impurity concentration of the N type column 26.
When the impurity concentration of the N type column 26 is increased, the impurity concentration of the P type column 24 is required to be increased. This is because the depletion layer expanding in the P type column 24 and the N type column 26 from the P-N junction surface may become imbalanced if the impurity concentration of the P type column 24 is not increased. Therefore, to deplete the drift region 23 completely, the column width of the N type column 26 is required to be smaller than that of the P type column 24. Each column width is defined by a pitch in the repeat direction. However, if the column width of the N type column 26 becomes small, a cross sectional area of the N type column 26 is reduced, so that it is difficult to reduce the resistance of the N type column 26.
Therefore, it is required that the impurity concentration of the P type column 24 is increased in accordance with increase of the impurity concentration of the N type column 26, and the column width of the P type column 24 is equalized to that of the N type column 26.
In the semiconductor device 1 shown in FIG. 1, as the drift resistance of the on state resistance becomes smaller, i.e., as the impurity concentration of the N type column 26 becomes higher, the impurity concentration of the P type column 24 becomes higher.
FIG. 2A is an enlarged perspective view showing around the trench gate electrode 36 of the semiconductor device 1 shown in FIG. 1. As described above, in a case where the impurity concentration of the P type column 24 is increased so as to reduce the drift resistance, a portion of the P type column 24 facing the trench gate electrode 36 is not reversed even when the positive voltage is applied to the trench gate electrode 36. The portion of the P type column 24 is shown as a region surrounded by a dashed line in FIG. 2A. Therefore, even when the inversion layer is formed in the body region 30 facing the trench gate electrode 36, a part of the inversion layer disposed on the upside of the P type column 24 does not flow current. FIG. 2B shows a state where the current does not flow in the part of the inversion layer. The portion of the body region 30 disposed on the P type column 24 hardly flow the current. The current only flows through the inversion layer of the body region 30, which faces the trench gate electrode 36 and is disposed on the N type column 26. Specifically, the current flows through a portion shown as a shadow area in FIG. 2B. Therefore, in the semiconductor device 1 shown in FIG. 1, the whole area of the inversion layer (i.e., the channel) of the body region 30 facing the trench gate electrode 36 does not work as a current path. Thus, the channel resistance does not become lower.
Another semiconductor device is disclosed in Japanese Patent Application Publication No. 2000-260984. In the semiconductor device, the impurity concentration of the N type column 26 is increased so that the resistance of the drift region 23 is reduced. Further, the inversion layer (i.e., the channel) formed in the body region 30 is effectively used for reducing the channel resistance. The semiconductor device includes an N type channel region disposed between the drift region 23 and the body region 30 in the super junction construction.
The N type channel region provides the current path between the inversion region disposed on the P type column 24 and the N type column 26 through the N type channel region. In this case, the inversion layer of the body region 30 facing the trench gate electrode 36, specifically, the inversion layer disposed on the P type column 24 can flow the current. Here, the inversion layer disposed on the P type column 24 in the semiconductor device 1 shown in FIG. 1 does not flow the current. Therefore, the channel resistance is decreased.
In the semiconductor device, the impurity concentration of the N type column 26 is increased so that the drift resistance is reduced. Further, the N type channel region provides to reduce the channel resistance. However, the semiconductor device necessitates the N type channel region. Further, a method for manufacturing the semiconductor device necessitates an additional process for forming the N type channel region.
Furthermore, the N type channel region causes a floating of electric potential in the P type column 24. When the potential of the P type column 24 is unstable, the P-N junction surface between the P type column 24 and the N type column 26 is not applied with sufficient voltage, so that the P type and N type columns 24, 26 may not be depleted. Thus, the withstand voltage is unstable.